1. Field of the Invention
The present invention relates to a CMOS or Bi-CMOS semiconductor device.
2. Description of the Related Art
A CMOS semiconductor device in which n- and p-channel MOSFETs are formed on a single chip is conventionally known. In addition, a Bi-CMOS semiconductor device obtained by adding a bipolar transistor to this CMOS semiconductor device is known.
Recently, LSI manufacturing techniques, especially, unit techniques such as oxidation, diffusion, etching, and exposure have significantly progressed. In accordance with this progress, the occupation area per element on a chip has decreased, and the packing density and operation speed of an LSI have increased. In the CMOS semiconductor device and the Bi-CMOS semiconductor device described above, micropatterning of an element has naturally progressed.
As micropatterning of an element has progressed, a film structure of an insulating film or a profile of an impurity concentration in a substrate, for example, in a semiconductor device has been largely improved to suppress generation of a leakage current, thereby ensuring reliability.
In recent years, however, the reliability of an apparatus for manufacturing an element has not followed the rapid progress in micropatterning of an element. In particular, a parasitic pnpn structure is formed inside an element in the CMOS and Bi-CMOS semiconductor devices. This pnpn structure operates similarly to a thyristor to cause a latch-up phenomenon of the CMOS semiconductor device or a so-called field inversion phenomenon in which a semiconductor layer immediately below a field oxide film is inverted, thereby degrading the reliability of an element. Especially when a CMOS or Bi-CMOS semiconductor device having a micro element structure is manufactured by using a VG (Vapor Growth) wafer as shown in FIG. 1 , a latch-up phenomenon caused by a parasitic pnpn structure significantly appears.
The VG wafer shown in FIG. 1 and its problems will be described below.
As shown in FIG. 1, n.sup.+ -type buried layers A(N.sup.+ B.L.) 122 and p.sup.+ -type buried layers (P.sup.+ B.L.) 123 are formed on a p-type semiconductor substrate 121, and an n-type epitaxial layer 124 is formed thereon.
In a method of manufacturing such a VG wafer, an oxide film or a photoresist is used as a mask to selectively vapor-phase-diffuse antimony (Sb) as an n-type impurity on the p-type semiconductor substrate 121, thereby forming the n.sup.+ -type buried layers 122. Similarly, an oxide film or a photoresist is used as a mask to selectively vapor-phase-diffuse boron (B) as a p-type impurity to form the p.sup.+ -type buried layers 123 on the substrate 121. The n-type epitaxial layer 124 is formed on the entire surface by a CVD method at a temperature of, e.g., 1,100.degree. C. to 1,250.degree. C. During this formation, however, boron (B) having a high diffusion coefficient is unnecessarily diffused in the n-type epitaxial layer 124, resulting in a dull profile of impurity concentration in the p.sup.+ -type buried layers 123.
FIG. 2 shows a profile of an impurity concentration of a section taken along a line 2--2 in FIG. 1. For comparison, FIG. 3 shows a profile of an impurity concentration of a section taken along a line 3--3 in FIG. 1. As is apparent from FIGS. 2 and 3, the impurity concentration of the p.sup.+ -type buried layers 123 is decreased by growing the n-type epitaxial layer 124. When the impurity concentration of the layers 123 is decreased, insulating performance of the n.sup.+ -type buried layers 122 formed in contact with the layers 123 is reduced which may cause a latch-up phenomenon. In order to solve this problem, an impurity concentration of the p.sup.+ -type buried layers 123 may be set higher in consideration of the fact that the profile of the impurity concentration becomes dull. In this case, however, the amount (unnecessary diffusion amount) of leakage of boron is further increased. An increase in boron leakage amount adversely affects an active element formed in the n-type epitaxial layer 124. For example, a threshold value varies in a MOSFET, or a withstand voltage is reduced or an early voltage is degraded in a bipolar transistor.
The above phenomenon occurs not only when an n-type epitaxial layer is formed as described above but also when a p-type epitaxial layer is formed.
In addition, leakage of boron having a high diffusion coefficient into an epitaxial layer occurs not only during formation of the epitaxial layer but also during a heating step (normally at 1,100.degree. C. to 1,250.degree. C.) for forming a well region in a epitaxial layer (not shown). This makes it more difficult to solve the above problem.